The present invention relates to signal paths in programmable logic devices generally and, more particularly, to high speed paths in programmable logic devices.
A programmable logic device (PLD) provides an economical and efficient means for implementing predetermined Boolean logic functions in an integrated circuit. Such a device consists of, generally, an AND plane configured to generate predetermined product terms in response to a plurality of inputs, a group of fixed/programmable OR gates configured to generate a plurality of sum-of-product(SOP) terms in response to the product terms, and a macrocell configured to generate a desired output in response to the sum-of-products terms. The sum-of-products terms can also be generated using programmable NOR-NOR logic.
In particular, such a macrocell may be programmed to operate in a combinatorial mode, where the output follows the input, delayed by the propagation delay of the macrocell. The macrocell may be further programmed to operate in a storage mode, where the output is a function of a clock signal (i.e., the macrocell output is synchronous with the clock signal). Moreover, other features available in connection with the operation of the macrocell, and which may be programmable, include the output polarity of the macrocell (i.e., whether the output is active high, or active low). The macrocell may be programmed to operate in the combinatorial mode or the storage mode, the storage mode including a latch mode, and a registered mode. In the registered mode, the macrocell may be programmed to operate as a flip-flop (e.g., a D-type flip-flop or a T-type flip-flop).
The AND plane of a PLD can be constructed using an array of memory cells arranged in rows and columns. Each of the plurality of inputs is presented to an input of the memory cells in a row. Each of the memory cells in a row is programmed to generate a signal in response to the particular input. An output of each of the memory cells in a column is connected to a sense amplifier. Each column of the array has a sense amplifier configured to generate one of the product terms in response to the signals generated by the memory cells in the column.
Referring to FIG. 1, a block diagram of a macrocell 10 illustrating a fast input path of a conventional PLD is shown. A PLD can have a fast input for implementing speed critical logic. The fast inputs are implemented separately from the AND plane inputs. For example, a fast input may be implemented by creating an alternative path that is shorter than the paths of other (i.e., normal) inputs. The macrocell 10 has a fast path 12 that connects an input pin 14 to a fast input select circuit 16, and a programmable register 18. The fast path 12 is separate from the inputs of an AND plane 20. Because the fast path 12 is separate from the AND plane 20, no logic functions can be performed on the fast input 14. Normal inputs connected to the macrocell 10 via the AND plane 20 can take full advantage of the logic capabilities of the AND plane. The macrocell 10 can be programmed for either the fast path or the normal combinatorial paths. Therefore, the fast path 14 requires a dedicated pin and a dedicated macrocell. In addition, the fast input provided by the macrocell 10 cannot provide an asynchronous fast input signal.
The present invention concerns an apparatus comprising two or more memory elements connected in parallel and programmed alike, where the memory elements comprise a high speed path of a programmable logic device.
The objects, features and advantages of the present invention include providing an architecture and/or method for implementing a high speed path in a programmable logic device that may (i) be built in a logic array by connecting an input to multiple non-volatile array cells, (ii) program multiple cells with identical data, (iii) produce more current to create a faster path than a normal input, (iv) use existing designs for non-volatile cells, (v) have lower RandD expenses for similar programming characteristics, (vi) fit in pitch with similar peripheral circuits, and/or (vii) provide same logic functions for high speed path and normal path.